1. Field of the Invention
The present invention generally relates to semiconductor random access memory. (RAM) devices and, more particularly, to a virtual multi-port RAM (VMPRAM) which combines multi-port RAM function with automatic port sequencing and single-port array density and speed.
2. Description of the Prior Art
Multi-port RAMs have been developed for high speed applications, such as real time signal processing or parallel data processing. In the former application, multi-port RAMs may be used as main memory to handle large amounts of data simultaneously. In the latter application, multi-port RAMs may be used as shared cache memory for a plurality of processors.
For example, U.S. Pat. No. 4,783,732 to Morton describes a multi-port memory including first and second memory lines. Each signal line can simultaneously and independently access a particular address during a read memory portion of a clock pulse whereas both signal lines are used to write data to one address during another portion of the clock pulse.
U.S. Pat. No. 4,766,535 to Auerbach et al. describes a multiple port memory responsive to addresses within an instruction cycle for supplying data read from the read addresses and for writing data received at the write addresses. The memory apparatus comprises groups of memory banks, responsive to the read addresses and the write addresses, for supplying for each of the read addresses data read from one of the banks in one of the groups and for writing data received at each of the write addresses in the other of the banks in the groups. A pointer for controlling the groups of memory banks directs the read and write accesses to the memory banks so that one of the banks obtaining valid data is read in response to a read address and so that data is written to the other banks in each cycle.
U.S. Pat. No. 4,740,894 to Lyon describes a processing element used either separately or in an array of similar processing elements for performing concurrent data processing calculations. The processing element includes a multi-ported memory unit for storing data to be processed by any of a plurality of function units which are connected to the multi-ported memory unit. The multi-ported memory unit includes a number of data storage slots for storing data words to be processed and the results of the processing. Each function unit performs a calculation having as its inputs one or more data words from the multi-ported memory unit. The result of this calculation is stored back in the multi-ported memory unit. The transfer of data to and from the function units is accomplished by use of the ports on the multi-ported memory unit.
T. Matsumura et al. in their paper entitled "Pipelined, Time-Sharing Access Technique for a Highly Integrated Multi-Port Memory", submitted to the 1990 VLSI Symposium, describe one attempt to provide a multi-port function using a consecutive time-sharing access technique. In their conceptual model, a four-port memory function is realized using a two-port memory cell array within one cycle. In the first half of the cycle, two-port memory cells are accessed simultaneously by addresses A.sub.0 and A.sub.2. The data D.sub.0 and D.sub.2 are written to the selected two-port memory cells or read out from them in parallel. In the second half of the cycle, the other two-port memory cells are selected concurrently by the addresses A.sub.1 and A.sub.3, and the data D.sub.1 and D.sub.3 are written to or read out in the same manner as before.
While the Matsumura et al. approach offers certain advantages, the two accesses executed to the memory during one cycle are timed externally and the access path is pipelined only relative to input and output latches. This limits the speed of the memory. In addition, the large, two-port memory cell used is a low density device which further limits the speed of the memory as well as its capacity. Moreover, any system using a memory employing the Matsumura et al. technique will have to resolve contention off the chip.
Multi-port access to a large, high speed data memory cache is the key to advanced parallel machine architectures. European Patent Application 0136218 published Apr. 3, 1985, discloses a horizontal computation device including a multi-port RAM in combination with independent pipelined memoryless junction modules. The device is operative to implement a class of algorithms involving a high ratio of arithmetic computation to control complexity and good locality of data reference. The memory structure is a parallel input, parallel output random access memory having a plurality of dedicated serial buffered input ports and dedicated serial buffered output ports. The buffered ports are operative to provide transient storage in independent pipelines and parallel input and output to addressed locations of the random access memory.
What is needed is an efficient multi-port function implemented in a high-speed, high-density RAM structure that approaches the speed and density of current single port RAM structures. A multi-port RAM of this type can be exploited in the design of many types of computers.